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flash memory 1 K9T1G08U0M preliminary document title 128m x 8 bits nand flash memory revision history the attached datasheets are prepared and approved by samsung el ectronics. samsung el ectronics co., ltd. reserve the right to change the specifications. sams ung electronics will evaluate and reply to y our requests and questions about device. if you h ave any questions, please contact the samsung branch office near you. revision no. 0.0 0.1 0.2 0.3 0.4 0.5 remark advanced preliminary preliminary preliminary preliminary preliminary history initial issue. tr is changed. [old : 12 s(max.), new :15 s(max.)] ce must be held low during tr added. 1. add the protrusion/burr value in wsop1 pkg diagram . 1. pkg(tsop1, wsop1) dimension change 1. technical note is changed 2.note1 of program/erase characteristics is added draft date aug. 7th 2003 oct. 20th 2003 mar. 9th 2004 apr. 24th 2004 may. 24th 2004 oct. 25th 2004 note : for more detailed features and specifications in cluding faq, please refer to samsung?s flash web site. http://www.samsung.com/products/semiconductor/
flash memory 2 K9T1G08U0M preliminary general description features ? voltage supply : 2.7v ~ 3.6v ? organization - memory cell array : (128m + 4,096k)bits x 8bits - data register : (512 + 16)bits x 8bits ? automatic program and erase - page program : (512 + 16)bits x 8bits - block erase : (16k + 512)bytes ? page read operation - page size : (512 + 16)bytes - random access : 15 s(max.) - serial page access : 50ns(min.) ? fast write cycle time - program time : 200 s(typ.) - block erase time : 2ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions 128m x 8 bits nand flash memory ? reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years ? command register operation ? intelligent copy-back ? unique id for copyright protection ? package - K9T1G08U0M-ycb0/yib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - K9T1G08U0M-vcb0/vib0 48 - pin wsop i (12 x 17 x 0.7mm) - K9T1G08U0M-pcb0/pib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch)- pb-free package - K9T1G08U0M-fcb0/fib0 48 - pin wsop i (12 x 17 x 0.7mm)- pb-free package * K9T1G08U0M-v,f(wsopi ), K9T1G08U0M-y,p(tsop1) is the same dev ice as except package type. offered in 128mx8bits, the K9T1G08U0M is 1gbit with spare 32mbit capacity. the device is offered in 3.3v vcc. its nand cell pro - vides the most cost-effective solution for the solid state ma ss storage market. a program operation can be performed in typical 200 s on the 528-bytes and an erase operation can be performed in typica l 2ms on a 16k-bytes block. data in the page can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data i nput/output as well as command input. the on-ch ip write control automates all program and eras e functions including pulse repetition, w here required, and internal verification a nd mar- gining of data. even the write-intensive sys tems can take advantage of the K9T1G08U0M s extended reliability of 100k program/ erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. the K9T1G08U0M is an optimum solution for large nonvolatile st orage applications such as solid state file storage and other por table applications requiring non-volatility. product list part number vcc range organization pkg type K9T1G08U0M-y,p 2.7v ~ 3.6v x8 tsop1 K9T1G08U0M-v,f wsop1
flash memory 3 K9T1G08U0M preliminary pin configuration (tsop1) K9T1G08U0M-ycb0,pcb0/yib0,pib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c package dimensions 48-pin lead/lead free plastic th in small out-line package type(i) 48 - tsop1 - 1220af unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 0.20 +0.07 -0.03
flash memory 4 K9T1G08U0M preliminary pin configuration (wsop1) K9T1G08U0M-vcb0,fcb0/vib0,fib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c dnu n.c n.c n.c r/b re ce dnu n.c vcc vss n.c dnu cle ale we wp n.c n.c dnu n.c n.c n.c n.c dnu n.c i/o7 i/o6 i/o5 i/o4 n.c dnu n.c vcc vss n.c dnu n.c i/o3 i/o2 i/o1 i/o0 n.c dnu n.c n.c package dimensions 48-pin lead plastic very very thin small out-line package type (i) 48 - wsop1 - 1217f unit :mm 15.40 0.10 #1 #24 0.20 +0.07 -0.03 0.16 +0.07 -0.03 0.50typ (0.50 0.06) #48 #25 0.10 +0.075 -0.035 17.00 0.20 0 ~ 8 0.45~0.75 12.00 0.10 0.58 0.04 0.70 max (0.01min) 12.40max
flash memory 5 K9T1G08U0M preliminary pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/ o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for comma nds sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase opertion. regarding ce control during read operation, refer to ?page read? section of device operation . re read enable the re input is the serial data-out control, and when acti ve drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the inter nal column address counter by one. we write enable the we input controls writes to the i/o port. comm ands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to hi gh state upon completion. it is an open drain output and does not float to high-z condition when the ch ip is deselected or when outputs are disabled. vccq output buffer power v cc q is the power supply for output buffer. vccq is internally connected to v cc, thus should be biased to vcc. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. dnu do not use leave it disconnected.
flash memory 6 K9T1G08U0M preliminary 512bytes 16 bytes figure 1. K9T1G08U0M functional block diagram figure 2. K9T1G08U0M array organization v cc x-buffers 1g + 32m bits command nand flash array (512 + 16)bytes x 262,144 y-gating page register & s/a i/o buffers & latches y-buffers control logic global buffers output driver v ss a 9 - a 26 a 0 - a 7 command ce re we wp i/0 0 i/0 7 v cc/ v ccq v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 256k pages (=8,192 blocks) 512 bytes 8 bits 16 bytes 1 block = 32 pages = (16k + 512) bytes i/o 0 ~ i/o 7 1 page = 528 bytes 1 block = 528 bytes x 32 pages = (16k + 512) bytes 1 device = 528bytes x 32pages x 8,192 blocks = 1,056 mbits column address row address (page address) page register cle ale note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low". * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 4th cycle a 25 a 26 *l *l *l *l *l *l register & high voltage generator latches & decoders latches & decoders
flash memory 7 K9T1G08U0M preliminary product introduction the K9T1G08U0M is a 1,056mbits(1,107,296,256 bits) memory organized as 262,144 rows(pages) by 528 columns. spare sixteen columns are located from column address of 512 to 527. a 528-bytes data register is connected to me mory cell arrays accommodat- ing data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structur e. each of the 16 cells resides in a different page. a block con sists of the 32 pages formed two nand structures. a nand structure consists of 16 cells. total 8,448 nand structures reside in a block. the array organization is shown in figure 2. the program and read operations are executed on a page basis, while the erase operatio n is executed on a block basis. the memo ry array consists of 8,192 separately erasable 16k-bytes blocks. it indicates that the bit b y bit erase operation is prohibited on the K9T1G08U0M. the K9T1G08U0M has addresses multiplexed into 8 i/o's. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintain ing consistency in system board design. command, address and data are all written throu gh i/o's by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respec tively, via the i/o pins. the 128m byte physical space requir es 27 addresses, thereby requiring four cycles for byte-level addressing : 1 cycle of colu mn address, 3 cycles of row address, in that order. page read and page program need the same four address cy cles following the required co mmand input. in block erase oper- ation, however, only the 3 cycles of row address are used. device operations are selected by writing specific commands into the com- mand register. table 1 defines the s pecific commands of the K9T1G08U0M. the device provides simultaneous program/erase capability up to four pages/blocks. by dividing the memory array into four 256mb it separate planes, simultaneous multi-plane oper ation dramatically increases program/erase performance by 4x while still maintain ing the conventional 512 bytes structure. the extended pass/fail status for multi-plane program/erase allows system software to qui ckly identify the failing page/block out of selected multiple pages/b locks. usage of multi-plane oper ations will be described furthe r through- out this document. in addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to anot her of the same plane without the need for transporting the data to and from the external buffer memory. since the time-consuming b urst- reading and data-input cycles are removed, system performance for soli d-state disk application is significantly increased. the device includes one block sized otp(one time programmable) , which can be used to increase system security or to provide identification capabilities. detailed informat ion can be obtained by contact with samsung. table 1. command sets note : 1. the 00h/01h command defines starting address of the 1st/2nd half of registers. after data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half reg ister(00h) on the next cycle. 2. page program(true) and copy-back program(true) are available on 1 plane operation. page program(dummy) and copy-back progra m(dummy) are available on the 2nd, 3rd, 4th plane of multi-plane operat ion. 3. the 71h command should be used for read status of multi plane operation. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1?st cycle 2?nd cycle 3?rd cycle 4?th cycle 5?th cycle acceptable command during busy read 1 00h/01h (1) ---- read 2 50h ---- read id 90h/91h ---- reset ffh ---- o page program (true) (2) 80h 10h - - - page program (dummy) (2) 80h 11h - - - copy-back program(true) (2) 00h 8ah 10h - - copy-back program(dummy) (2) 03h 8ah 11h - - block erase 60h d0h - - - multi-plane block erase 60h----60h d0h - - - read status 70h ---- o read multi-plane status 71h (3) ---- o
flash memory 8 K9T1G08U0M preliminary the device is arranged in four 256mbits memory planes. each plane contains 2,048 bl ocks and 528 bytes page register. this allow s it to perform simultaneous page program and block erase by sele cting one page or block from each plane. the block address map i s configured so that multi-plane program/erase operati ons can be executed for ever y four sequential blocks. plane 0 plane 1 plane 2 plane 3 (2,048 blocks) (2,048 blocks) (2,048 blocks) (2,048 blocks) page 0 page 1 page 31 page 30 memory map block 0 page 0 page 1 page 31 page 30 block 1 page 0 page 1 page 31 page 30 block 2 page 0 page 1 page 31 page 30 block 3 page 0 page 1 page 31 page 30 block 4 page 0 page 1 page 31 page 30 block 5 page 0 page 1 page 31 page 30 block 6 page 0 page 1 page 31 page 30 block 7 page 0 page 1 page 31 page 30 block 8,184 page 0 page 1 page 31 page 30 block 8,185 page 0 page 1 page 31 page 30 block 8,186 page 0 page 1 page 31 page 30 block 8,187 page 0 page 1 page 31 page 30 block 8,188 page 0 page 1 page 31 page 30 block 8,189 page 0 page 1 page 31 page 30 block 8,190 page 0 page 1 page 31 page 30 block 8,191 528bytes page register figure 3. memory array map 528bytes page register 528bytes page register 528bytes page register
flash memory 9 K9T1G08U0M preliminary dc and operating characteristics (recommended operating cond itions otherwise noted.) notes : 1. typical values are measured at vcc=3.3v, t a =25 c. and not 100% tested. paramete symbol test conditions min typ max unit operating current sequential read i cc 1 trc=50ns, ce =v il, i out =0ma - 10 20 ma program i cc 2- -1020 erase i cc 3- -1020 stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1 stand-by current(cmos) i sb 2ce =v cc -0.2, wp =0v/v cc -1050 a input leakage current i li v in =0 to vcc(max) - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 input high voltage v ih i/o pins 2.0 - v ccq +0.3 v except i/o pins 2.0 - v cc +0.3 input low voltage, all inputs v il --0.3-0.8 output high voltage level v oh i oh =-400 a2.4-- output low voltage level v ol i ol =2.1ma - - 0.4 output low current(r/b )i ol (r/b )v ol =0.4v 8 10 - ma recommended operating conditions (voltage reference to gnd at the condision of K9T1G08U0M-xcb0 : t a =0 to 70 c or K9T1G08U0M-xib0 : t a =-40 to 85 c) parameter symbol min typ. max unit supply voltage v cc 2.7 3.3 3.6 v v ccq 2.7 3.3 3.6 v v ss 000v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rati ng conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to vss v in/out -0.6 to +4.6 v v cc/ v ccq -0.6 to +4.6 temperature under bias K9T1G08U0M-xcb0 t bias -10 to +125 c K9T1G08U0M-xib0 -40 to +125 storage temperature t stg -65 to +150 c short circuit current i os 5ma
flash memory 10 K9T1G08U0M preliminary capacitance ( t a =25 c, v cc =3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the K9T1G08U0M may include invalid blocks when first shipped . additional invalid blocks may develop while being used. the nu mber of valid blocks is presented with both cases of invalid blocks considered. invali d blocks are defined as blocks that contain one or more bad bi ts. do not erase or program factory-marked bad blocks. refer to the attached techni cal notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fu lly guaranteed to be a valid block, does not require error correc tion up to 1k program/erase cycles. 3. minimum 2,013 valid blocks are guaranteed for each contiguous 256mb memory space. parameter symbol min typ. max unit valid block number n vb 8,052 - 8,192 blocks ac test condition (K9T1G08U0M-xcb0 :ta=0 to 70 c, k9t1gxxu0m-xib0:ta=-40 to 85 c) parameter value input pulse levels 0.4v to 2.4v input rise and fall times 5ns input and output timing levels 1.5v output load vccq=3.0v+/-10% : 1 ttl gate and cl= 50pf vccq=3.3v+/-10% : 1 ttl gate and cl=100pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hll hx read mode command input l h l h x address input (4 clocks) hll hh write mode command input l h l h h address input (4 clocks) l l l h h data input l l l h x data output l l l h h x during read (busy) x x x x x h during program (busy) x x x x x h during erase (busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by program / erase characteristics parameter symbol min typ max unit program time t prog (1) - 200 500 s dummy busy time for multi plane program t dbsy 110 s number of partial program cycles in the same page main array nop - - 1 cycle spare array - - 2 cycle block erase time t bers -23ms note : 1.typical program time is defined as the time within more than 50% of the whole pages are programmed at vcc of 3.3v and 25 c
flash memory 11 K9T1G08U0M preliminary ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. 2. to break the sequential read cycle, ce must be held high for longer time than tceh. 3. the time to ready depends on the value of the pull-up resistor tied r/b pin. parameter symbol min max unit data transfer from cell to register t r -15 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 25 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns ce access time t cea -45ns re access time t rea -30ns re high to output hi-z t rhz -30ns ce high to output hi-z t chz -20ns re or ce high to output hold t oh 15 - ns re high hold time t reh 15 - ns output hi-z to re low t ir 0-ns we high to re low t whr 60 - ns device resetting time (read/program/erase) t rst - 5/10/500 (1) s last re high to busy(at sequential read) t rb - 100 ns ce high to ready(in case of interception by ce at read) t cry - 50 + tr(r/b ) (3) ns ce high hold time(at the last serial read) (2) t ceh 100 - ns ac timing characteristics for command / address / data input note : 1. if tcs is set less than 10ns, twp must be mi nimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol min max unit cle set-up time t cls 0-ns cle hold time t clh 5-ns ce setup time t cs 0.-ns ce hold time t ch 5-ns we pulse width t wp 25 (1) -ns ale setup time t als 0-ns ale hold time t alh 5- ns data setup time t ds 20 - ns data hold time t dh 5-ns write cycle time t wc 45 - ns we high hold time t wh 15 - ns
flash memory 12 K9T1G08U0M preliminary nand flash technical notes identifying initial invalid block(s) initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is so call ed as the initial invalid block information. devices with init ial invalid block(s) have the same quality level as devic es with all valid blocks and have the same ac and dc characteristics. an initial i nvalid block(s) does not affect the performance of valid block(s) bec ause it is isolated from the bit line and the common source line by a select transistor. the system design must be able to mask out the initial invalid block(s) vi a address mapping. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correction up to 1k program/erase cycles. all device locations are erased(ffh) except locations where the initial invalid block(s) information is written prior to shippi ng. the initial invalid block(s) status is defined by the 6th byte in the spare area. samsung makes sure that either the 1st or 2nd pag e of every initial invalid block has non-ffh data at the column addre ss of 517. since the initial in valid block information is also erasable in most cases, it is impossible to recover the information onc e it has been erased. therefore, the system must be able to recog nize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following sug- gested flow chart(figure 4). any intentional erasure of the initial invalid block information is prohibited. * check "ffh" at the column address 517 figure 4. flow chart to create initial invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no initial invalid block(s) table of the 1st and 2nd page in the block
flash memory 13 K9T1G08U0M preliminary nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes error in write or read operation within its life time, the additional invali d blocks may develop with nand flash memory . refer to the qualification report for t he block failure rate.the following possible failur e modes should be considered to implement a highly reliable system. in the case of st atus read failure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block repl acement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and c opying the rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of memory space, it is recommended that the read failure due to single bit error sh ould be reclaimed by ecc without any block repl acement. the block failure rate in the qual ification report does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read af ter erase --> block replacement program failure status read after program --> block replacement read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bits detection : if program operation results in an error, map out the block including the page in error and copy the * target data to another block.
flash memory 14 K9T1G08U0M preliminary erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1. when an error happens in the nth page of th e block ?a? during erase or program operation. * step2. copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3. then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4. do not further erase block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { 1st (n-1)th nth (page) { an error occurs.
flash memory 15 K9T1G08U0M preliminary samsung nand flash has three address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command sets the pointer to ?b? area(256~511byte), and ?50h? command set s the pointer to ?c? area(512~527byte). with these commands, the starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another address pointer command is inputted. ?01h? command, however, is effe ctive only for one operation. after any operation of read, program, erase, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data st arting from ?a? or ?c? area, ?00h? or ?50h? command must be in putted before ?80h? command is written. a complete read operation prio r to ?80h? command is not necessary. to program data starting fr om ?b? area, ?01h? command must be inputted right before ?80h? command is written. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~511), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of K9T1G08U0M table 2. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 bytes (00h plane) "b" area (01h plane) "c" area (50h plane) 256 bytes 16 bytes "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 5. block diagram of pointer operation
flash memory 16 K9T1G08U0M preliminary system interface using ce don?t-care. ce we t wp t ch t cs start add.(4cycle) 80h data input ce cle ale we i/o x data input ce don?t-care 10h for an easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the internal 528bytes page registers are utilized as separate buffers for this operation and the system design gets more flexible. in additi on, for voice or audio applications which us e slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant savings in power consumption. start add.(4cycle) 00h ce cle ale we i/o x data output(sequential) ce don?t-care r/b t r re t cea out t rea ce re i/o x figure 6. program operation with ce don?t-care. figure 7. read operation with ce don?t-care. ce must be held low during tr
flash memory 17 K9T1G08U0M preliminary * command latch cycle ce we cle ale i/o x command * address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh ce we cle ale i/o x a0~a7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t alh t ds t dh t wp a9~a16 a17~a24 a25~a26
flash memory 18 K9T1G08U0M preliminary * input data latch cycle ce cle we din 0 din 1 din n ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp * serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. i/ox i/ox t chz* t rhz*
flash memory 19 K9T1G08U0M preliminary t chz t oh * status read cycle ce we cle re i/o x 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr t cea t cls read1 operation (read one page) ce cle r/b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 column address page(row) address t wb t ar t r t rc t rhz t rr dout m t rb t cry t wc a 25 ~ a 26 t ceh n address t chz t rhz t oh
flash memory 20 K9T1G08U0M preliminary read1 operation (intercepted by ce ) ce cle r/b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 page(row) address address column t wb t ar t chz t r t rr t rc read2 operation (read one page) ce cle r/b i/o x we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n+m m address n+m t ar t r t wb t rr a 0 ~a 3 : valid address a 4 ~a 7 : don t care a 25 ~ a 26 a 25 ~ a 26 selected row start address m 512 16 t oh
flash memory 21 K9T1G08U0M preliminary page program operation ce cle r/b i/o x we ale re 80h 70h i/o 0 din n din 10h 527 a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc sequential row read operation ( within a block ) ce cle r/b i/o x we ale re 00h a 0 ~ a 7 busy m output a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout 527 dout 0 dout 1 dout 527 busy m+1 output n ready a 25 ~ a 26 a 25 ~ a 26
flash memory 22 K9T1G08U0M preliminary block erase operation (erase one block) ce cle r/b i/o x we ale re 60h a 17 ~ a 24 a 9 ~ a 16 erase setup command erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc a 25 ~ a 26
flash memory 23 K9T1G08U0M preliminary t prog t dbsy t dbsy t dbsy twb tprog tdbsy twb multi-plane page program operation ce cle r/b i/o x we ale re 80h din n din 11h m a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program max. three times repeatable twc a 25 ~ a 26 command last plane input & program t dbsy : typ. 1us max. 10us (dummy) din n din 10h 527 a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 a 25 ~ a 26 i/o 80h a 0 ~ a 7 & a 9 ~ a 26 i/o 0 ~ 7 r/b 528 byte data address & data input 11h 80h address & data input 11h 80h address & data input 11h 80h address & data input 10h ex.) four-plane page program program confirm command (true) 80h 71h 71h read multi-plane status command a 0 ~ a 7 & a 9 ~ a 26 528 byte data a 0 ~ a 7 & a 9 ~ a 26 528 byte data a 0 ~ a 7 & a 9 ~ a 26 528 byte data
flash memory 24 K9T1G08U0M preliminary multi-plane block erase operation erase setup command erase confirm command read multi-plane status command max. 4 times repeatable 60h a 9 ~ a 26 i/o 0 ~ 7 r/b address 60h a 9 ~ a 26 60h a 9 ~ a 26 60h a 9 ~ a 26 d0h 71h t bers * for multi-plane erase operation, block address to be erased should be repeated before "d0h" command. ex.) four-plane block erase operation ce cle r/b i/o x we ale re 60h a 17 ~ a 24 a 9 ~ a 16 doh 71h i/o 0 busy t wb t bers page(row) address t wc a 25 ~ a 26 i/o 0 =1 error in erase i/o 0 =0 successful erase
flash memory 25 K9T1G08U0M preliminary read id operation (90 id) ce cle i/o x we ale re 90h read id command maker code device code 00h ech 79h t rea address. 1cycle a5h c0h multi plane code id defintition table 90 id : access command = 90h value description 1 st byte 2 nd byte 3 rd byte 4 th byte ech 79h a5h c0h maker code device code must be don?t -cared supports multi plane operation read id operation (91 id) ce cle i/o x we ale re 91h read id command extended id code 00h 20h t rea address. 1cycle
flash memory 26 K9T1G08U0M preliminary copy-back program operation ce cle r/b i/o x we ale re 00h 70h i/o 0 8ah a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address busy t wb t r a 25 ~a 26 10h copy-back data input command busy a 25 ~a 26
flash memory 27 K9T1G08U0M preliminary device operation page read upon initial device power up, the device defaults to read1 mode. th is operation is also initiated by writing 00h to the command regis- ter along with four address cycles. once the command is latched, it does not need to be written for the following page read ope ration. three types of operations are available : r andom read, serial page read and sequential row read. the random read mode is enabled when the page address is changed. t he 528 bytes of data within the selected page are transferre d to the data registers in less than 15 s(t r ). the system controller can detect the comple tion of this data transfer(tr) by analyzing the output of r/b pin. if ce goes high before the device returns to ready, the random read operation is interrupted and busy returns to ready as the defined by tcry. since the operation was aborted, the serial page read does not output valid data. once the data i n a page is loaded into the registers, they may be r ead out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data stating from the selected column address up to the last column address. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of 51 2 to 527 byte may be selectively accessed by writing the read2 command. addresses a 0 to a 3 set the starting address of the spare area while addresses a 4 to a 7 are ignored. the read1 command(00h/01h) is needed to move the pointer back to the main area. fig- ures 8 to 10 show typical sequence and timings for each read operation. after the data of last column address is clocked out, the next page is automatically selected fo r sequential row read. waiting 12 s again allows reading the selected page. the sequentia l row read operation is terminated by bringing ce high. unless the operation is aborted, the page address is automatically incremented for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the sequential read 1 and 2 oper ation is allowed only within a block and after the last p age of a block is readout, the sequential read operation must be terminated by bringing ce high. when the page address moves onto the next block, read command and address must be given. figures 9, 10 show typical sequence and timings for sequential row read operation. figure 8-1. read1 operation start add.(4cycle) 00h data output(sequential) ce cle ale r/b we i/o 0 ~ 7 re t r a 0 ~ a 7 & a 9 ~ a 26 (00h command) data field spare field main array (01h command) data field spare field 1st half array 2st half array note : 1) after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at nex t cycle. 1)
flash memory 28 K9T1G08U0M preliminary figure 8-2. read2 operation 50h data output(sequential) spare field ce cle ale r/b we start add.(4cycle) i/o x re figure 9. sequential row read1 operation 00h 01h a 0 ~ a 7 & a 9 ~ a 26 i/o x r/b start add.(4cycle) data output data output data output 1st 2nd nth (528 byte) (528 byte) t r t r t r t r the sequential read 1 and 2 operation is allowed only within a block and after the last page of a block is read- out, the sequential read operation mu st be terminated by bringing ce high. when the page address moves onto the next block, read command and address must be given. ( 00h command) data field spare field ( 01h command) data field spare field 1st half array 2nd half array 1st 2nd nth 1st half array 2nd half array 1st 2nd nth block a 0 ~ a 3 & a 9 ~ a 26 main array data field spare field (a 4 ~ a 7 : don?t care)
flash memory 29 K9T1G08U0M preliminary figure 10. sequential row read2 operation page program the device is programmed basically on a page ba sis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 byte, in a single page program cycle. the number of consecutive partial page programmi ng operation within the same pa ge without an intervening erase operation must not exceed 1 for main array and 2 for spare array. the addressing may be done in an y random order in a block. a page program cycle consists of a se rial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming per iod where the loaded data is programmed into the appropriate cell. serial data loading can be started from 2nd half array by moving pointer. about the pointer operation, please refer to the atta ched technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the four cycle address input and then serial data loading. the bytes other than those to be pr ogrammed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate th e pro- gramming process. the internal write state control automatically executes the algorithms and timi ngs necessary for program and verify, thereby freeing the system controll er for other tasks. once the program proc ess starts, the read status register comman d may be entered, with re and ce low, to read the status register. the system c ontroller can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0) may be checked(figure 11 ). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remai ns in read status command mode until another valid command is written to the command register. 50h a 0 ~ a 3 & a 9 ~ a 26 i/o x r/b start add.(4cycle) data output data output data output 2nd nth (16byte) (16byte) 1st figure 11. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 26 i/o 0 ~ 7 r/b address & data input i/o 0 pass 528 bytes data 10h 70h fail t r t r t r t prog data field spare field 1st block (a 4 ~ a 7 : don?t care) nth
flash memory 30 K9T1G08U0M preliminary figure 12. block erase operation block erase the erase operation is done on a block(16k byte s) basis. block address loading is accomp lished in three cycles initiated by an erase setup command(60h). only address a 14 to a 26 is valid while a 9 to a 13 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing proce ss. this two-step sequence of setup followed by execution command ensures that memory contents are not accident ally erased due to exte rnal noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bi t(i/o 0) may be checked. figure 12 details the sequence. 60h block add. : a 14 ~ a 26 i/o x r/b address input(3cycle) i/o 0 pass d0h 70h fail t bers multi-plane page program multi-plane page program is an extension of page program, which is executed for a single plane with 528 bytes page register. si nce the device is equipped with four memory planes, activating the f our sets of 528 bytes page register enables a simultaneous prog ram- ming of four pages. partial activati on of four planes is also permitted. after writing the first set of data up to 528 byte into the selected page register, dummy page program command (11h) instead of actual page program (10h) is inputted to finish data-loading of the current plane and move to the next plane. since no programm ing process is involved, r/b remains in busy state for a short period of time(tdbsy). read status command (standard 70h or alternate 71h) may be issued to find out when the device returns to ready state by polling the ready/busy status bit(i/o 6). then the nex t set of data for one of the other planes is inputted with the same command and address sequences. after inputting data for the last plane, actual true page program (10h) instead of dumy page program comm and (11h) must be followed to start the programming process. the operation of r/b and read status is the same as that of page progr am. since maximum four p ages are programmed simulta- neously, pass/fail status is available for each page when the pr ogram operation completes. the extended status bits (i/o1 throu gh i/ o 4) are checked by inputting the read multi-plane status register . status bit of i/o 0 is set to "1" when any of the pages fai ls. multi- plane page program with "01h" pointer is not supported, thus prohibited. figure 13. four-plane page program 80h 11h 80h 11h 80h 11h 80h 10h data input plane 0 plane 1 plane 2 plane 3 (2,048 blocks) (2,048 blocks) (2,048 blocks) (2,048 blocks) block 0 block 4 block 8,188 block 8,184 block 1 block 5 block 8,189 block 8,185 block 2 block 6 block 8,190 block 8,186 block 3 block 7 block 8,191 block 8,187 80h a 0 ~ a 7 & a 9 ~ a 26 i/o x r/b 528 bytes address & data input 11h 80h address & data input 11h 80h address & data input 11h 80h address & data input 10h t dbsy t dbsy t dbsy t prog 71h
flash memory 31 K9T1G08U0M preliminary restriction in addressing with multi plane page program while any block in each plane may be addressable for multi-plane pa ge program, the five least signi ficant addresses(a9-a13) for the selected pages at one operation must be the same. figu re 14 shows an example where 2nd page of each addressed block is selected for four planes. however, any arbitrary sequence is allowed in addressing multiple planes as shown in figure15. 80h plane 2 11h 80h 11h 80h 11h 80h 10h plane 0 plane3 plane 1 plane 0 plane 1 plane 2 plane 3 (2,048 blocks) (2,048 blocks) (2,048 blocks) (2,048 blocks) page 0 page 1 page 31 page 30 block 0 page 0 page 1 page 31 page 30 block 1 page 0 page 1 page 31 page 30 block 2 page 0 page 1 page 31 page 30 block 3 figure 16. multi-plane page program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 26 i/o 0 ~ 7 r/b address & data input i/o pass 10h 71h fail t prog last plane input multi-plane block erase basic concept of multi-plane block erase oper ation is identical to that of multi-pl ane page program. up to four blocks, one fro m each plane can be simultaneously erased. standar d block erase command sequences (block erase setup command followed by three address cycles) may be repeated up to four times for erasing up to four blocks. only one block sh ould be selected from each pla ne. the erase confirm command initiates the actual erasing process. the completion is detected by analyzing r/b pin or ready/busy status (i/o 6). upon the erase completion, pass/fail status of each block is examined by readi ng extended pass/fail status(i/o 1 through i/o 4). figure 17. four block erase operation 60h a 0 ~ a 7 & a 9 ~ a 26 i/o x r/b address 60h 60h 60h d0h 71h i/o pass fail t bers (3 cycle) address (3 cycle) address (3 cycle) address (3 cycle) figure 14. multi-plane program & read status operation figure 15. addressing multiple planes 528 bytes
flash memory 32 K9T1G08U0M preliminary copy-back program figure 18. 1-page copy-back program operation 00h a 0 ~ a 7 & a 9 ~ a 26 i/o x r/b add.(4cycles) i/o 0 pass 8ah 70h fail a 0 ~ a 7 & a 9 ~ a 26 add.(4cycles) t r source address destination address the copy-back program is configured to qui ckly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an exte rnal memory. since the time-consuming se quently-reading and its re-loading cycles are removed, the system performance is improved. the benefit is es pecially obvious when a portion of a block is updated and the res t of the block also need to be copied to the newly assigned free block. the operation for performing a copy-back program is a sequen tial execution of page-read without burst-reading cycle and copying-pr ogram with the address of destination page. a normal read oper a- tion with "00h" command and the address of the source page moves the whole 528bytes data into the internal page registers. as soon as the device returns to ready state, page-copy data-input command (8ah) with t he address cycles of destination page fol- lowed may be written. the program confirm command (10h) is re quired to actually begin the pr ogramming operation. copy-back program operation is allowed only within the same memory plane. once the copy-back program is finished, any additional partial page programming into the copied pages is prohibited before erase. a14 and a15 must be the same between source and target page. figure18 shows the command sequence for single plane operation. "when there is a program-failure at copy-back opera- tion, error is reported by pass/fail status. but, if copy-back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. for this reason, two bit error correction is recom- mended for the use of copy-back operation." 10h t prog
flash memory 33 K9T1G08U0M preliminary multi-plane copy-back program multi-plane copy-back program is an extension of one page copy -back program into four plane operation. since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous multi-plane copy- back programming of four pages. partial ac tivation of four planes is also permitted. first, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal page buffers. any further read operation for transferring the addr essed pages to the corresponding page register must be execut ed with "03h" command instead of "00h" command. any plane may be selected without regard to "00h" or "03h". up to four planes may be addressed. data moved into the internal page registers ar e loaded into the destination plane addresses. after the input of c om- mand sequences for reading the source pages, the same proc edure as multi-plane page programmi ng except for a replacement address command with "8ah" is executed. since no programming process is involved during data loading at the destination plane address , r/b remains in busy state for a short period of time(td bsy). read status command (standard 70h or alternate 71h) may be issued to find out when the device returns to ready state by polling the ready/busy status bit(i/o 6). after inputting data for the last plane, actual true page program (10h) instead of dummy p age program command (11h) must be followed to start the program- ming process. the operation of r/b and read status is the same as that of p age program. since maximum four pages are pro- grammed simultaneously, pass/fail status is available for each page when the program operation completes. no pointer operation is supported with multi-plane copy-back program. once the multi-plane copy-back program is finished, any additional partial page programming into the copied pages is prohibited before erase once the multi-plane copy-back program is finished. figure 19. 4-plane copy-back program 8ah 11h 8ah 11h 8ah 11h 8ah 10h destination plane 0 plane 1 plane 2 plane 3 (2,048 blocks) (2,048 blocks) (2,048 blocks) (2,048 blocks) block 0 block 4 block 8,188 block 8,184 block 1 block 5 block 8,189 block 8,185 block 2 block 6 block 8,190 block 8,186 block 3 block 7 block 8,191 block 8,187 00h 03h 03h 03h source plane 0 plane 1 plane 2 plane 3 (2,048 blocks) (2,048 blocks) (2,048 blocks) (2,048 blocks) block 4 block 8,188 block 8,184 block 5 block 8,189 block 2 block 6 block 8,190 block 8,186 block 3 block 7 block 8,191 block 8,187 address address input input block 0 block 1 block 4089 block 8,185 max three times repeatable max three times repeatable
flash memory 34 K9T1G08U0M preliminary 00h a 0 ~ a 7 & a 9 ~ a 26 i/o x r/b source address add.(4cyc.) 03h fig 20. four-plane copy-back page program (continued) t r a 0 ~ a 7 & a 9 ~ a 26 destination address add.(4cyc.) 11h 71h a 0 ~ a 7 & a 9 ~ a 26 source address add.( 4cyc.) 8ah 03h a 0 ~ a 7 & a 9 ~ a 26 source address add.( 4cyc.) a 0 ~ a 7 & a 9 ~ a 26 destination address add.(4cyc.) 11h 8ah a 0 ~ a 7 & a 9 ~ a 26 destination address add.(4cyc.) 10h 8ah t r t prog max. 4 times ( 4 cycle source address input) repeatable max. 4 times (4 cycle destination address input) repeatable tr : normal read busy tdbsy : typical 1us, max 10us t r t dbsy t dbsy
flash memory 35 K9T1G08U0M preliminary read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. af ter writing 70h command to the co mmand register, a read cycle outpu ts the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 4 fo r specific status register definitions. the command register remains in status read mode until further commands are issued to i t. therefore, if the status register is read during a random read cycle, a read command(00h or 50h) shoul d be given before sequential page read cycle. for read status of multi plane program/erase, the read mu lti-plane status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. the pass/fail status data must be checked only in the ready conditi on after the completion of multi-plane program or erase operatio n. table4. read staus register definition note : 1. i/o 0 describes combined pass/fail condi tion for all planes. if any of the selected multiple pages/blocks fails in program/ erase operation, it sets "fail" flag. 2. the pass/fail status applies only to the corresponding plane. i/o no. status definition by 70h command definition by 71h command i/o 0 total pass/fail pass : "0" fail : "1" pass : "0" (1) fail : "1" i/o 1 plane 0 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 2 plane 1 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 3 plane 2 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 4 plane 3 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 5 reserved must be don?t -cared must be don?t-cared i/o 6 device operation busy : "0" ready : "1" busy : "0" ready : "1" i/o 7 write protect protected : "0" not protected : "1" protected : "0" not protected : "1" read id the device has 2 types of read id command, i.e. read id (1) command 90h and read id (2) command 91h. the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. four read cycles sequentially output the manufacture c ode(ech), and the device code (79h), reserved(a5h), multi plane oper - ation code(c0h) respectively. a5h must be don?t-cared. c0h means that device supports multi plane operation. the command regis- ter remains in read id mode until further commands are issued to it. read id (2) command 91h provides multi-plane(4-plane) operations av ailability. if id code read out by 91h is 20h, it indicates the device has multi-plane(4-plane) operations. figure 21-1 & 21-2 show the operation sequence. figure 21-1. read id (1) operation ce cle i/o 0 ~ 7 ale re we 90h 00h ech address. 1cycle maker code device code t cea t ar t rea a5h c0h multi-plane code t whr 79h
flash memory 36 K9T1G08U0M preliminary figure 21-2. read id (2) operation ce cle i/o 0 ~ 7 ale re we 91h 00h 20h address. 1cycle extended id code t cea t ar t rea t whr figure 22. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort thes e operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 5 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/b pin transitions to low for trst after the reset command is written. refer to figure 22 below. after power-up after reset operation mode read 1 waiting for next command ffh i/o 0 ~ 7 r/b table5. device status t rst
flash memory 37 K9T1G08U0M preliminary ready/busy the device has a r/b output that provides a hardware method of indica ting the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal controller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obta ined with the following reference chart(fig 23). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp tr,tf [s] ibusy [a] rp(ohm) fig 23 rp vs tr ,tf & rp vs ibusy ibusy tr ibusy busy ready vcc @ vcc = 3.3v, ta = 25 c , c l = 100pf voh tf tr 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 100 tf 200 300 400 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 vol where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maxi mum permissible limit of tr rp(min) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l v ol : 0.4v, v oh : 2.4v c l
flash memory 38 K9T1G08U0M preliminary the device is designed to offer protection from any involuntary program/erase during pow er-transitions. an internal voltage de tector disables all functions whenev er vcc is below about 2v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 10 s is required before internal ci rcuit gets ready for any command sequences as shown in figure 24. the two step command sequenc e for program/erase provides additional software protection. figure 24. ac waveforms for power transition v cc wp high we data protection & power-up sequence ~ 2.5v ~ 2.5v 10 s

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